1. Field of the Invention
The present invention relates to a gate array type semiconductor device with MOS transistors arranged in array on a semiconductor layer.
2. Background of the Invention
The gate array type semiconductor device has been in wide use as a technique for providing an LSI in a short development period of time. This gate array type semiconductor device is previously formed halfway toward completion through a step (called a master step) of forming a semiconductor region and a gate electrode which form each of the MOS transistors (usually a pair of PMOS and NMOS transistors) arranged in array.
Each element or MOS transistor, which may be a pair of PMOS and NMOS transistors, at this stage is called a basic cell. Then, through a step (called a slice step) of forming a contact hole or a via hole and then a wiring pattern on each basic cell according to the user's order, the semiconductor device is made as a customized LSI. The components such as the contact hole or the wiring pattern formed on each basic cell through the slice step is called a macro cell.
In this fashion, the semiconductor device is previously prepared halfway toward completion through the master step common in various LSI manufacturing. This allows the gate array technique to manufacture various customized LSIs in a shorter development period of time as compared with a full-customizing technique wherein every step is executed according to the user's order.
By the way, attention is now focused on the fact that the MOS transistor formed on the semiconductor layer (SOI (Semiconductor on Insulator) layer) stacked on the surface of a buried insulating layer (generally consisting of oxide) has smaller parasitic capacitance than the MOS transistor formed on a semiconductor substrate of a bulk, thereby achieving high-speed operation and low power consumption.
Further, attention is also given to a recently introduced body control type SOI-CMOS circuit with a gate electrode connected to a body electrode, for achieving high-speed operation even at an extremely low voltage, for example, 0.5 V (c.L "1996 IEEE International Solid-State Circuit Conference" pp. 84-85, pp. 88-89, "1997 IEEE International Solid-State Circuit Conference" pp. 286-287). This transistor and circuit are, however, only the semiconductor devices manufactured by the full-customizing technique (a full-customized semiconductor device), so that the achievement of various kinds of LSIs will require quite a long development period of time.